Sometimes you need a set/reset flip flop and you have only one macrocell left for the task - one that has no register available. With this little trick you can do it.

The idea is very simple: You feed back the current output to 2 of the AND gates that contribute (via the OR gate) to the output. Depending on the state of another input of these AND gates (one for each) the state of the output is maintained or set to the correct state. Below is an example in CUPL. For users who do not know the syntax and the operators, here a brief overview:

Logical Operators
# OR
! Negation
Output Assignments
They are done with a simple assignment.

Here the lines you have to write to get it done: (Pin declarations omitted)


How does it work? Let us assume MYOUT is inactive and both input signals (MYIN_A and MYIN_B) are false, too. So, the second product term (that after the OR) can never become true, as it is the AND of MYOUT and some other. But the first term will become true when MYIN_A becomes true. Then MYOUT will go active and will disable the first term by this. But now the second term is "switched in". Both of it's input conditions are true, holding MYOUT active. But as soon as MYIN_B becomes active the second term no longer is true and MYOUT goes to the inactive state again. Remember, all signal names are only names of signals, not pins. You can derive them from pins or other parts of the logic. Only MYOUT (in a GAL) has to be a real output or an internal node must be used for it.

© Paul Elektronik, 1998-2002